U.S. Pat. No. 5,643,822 (IBM, 1997), incorporated by reference in its entirety herein, discloses a method for forming trench-isolated field effect transistor (FET) devices.
The transistor is a solid state semiconductor device which can be used for amplification, switching, voltage stabilization, signal modulation and many other functions. Generally, a transistor has three terminals, and a voltage applied to a specific one of the terminals controls current flowing between the other two terminals.
The terminals of a field effect transistor (FET) are commonly named source, gate and drain. In the FET, a small amount of voltage is applied to the gate (G) in order to control current flowing between the source (S) and drain (D). In FETs, the main current appears in a narrow conducting channel formed near (usually primarily under) the gate. This channel connects electrons from the source terminal to the drain terminal. The channel conductivity can be altered by varying the voltage applied to the gate terminal or by enlarging or constricting the conducting channel and thereby controlling the current flowing between the source and the drain.
FIGS. 1A and 1B illustrate an exemplary, conventional field effect transistor (FET) 100. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken on a line 1B-1B through FIG. 1A.
The FET 100 is formed upon a semiconductor substrate 102, and more particularly within a cell well (CW) portion of the substrate 102. The cell well (CW) is a region of the substrate 102 which has been doped, for example, to be an “n-well” within a “p-type” substrate.
The term “substrate” as used herein is intended to include a semiconductor substrate, a semiconductor epitaxial layer deposited or otherwise formed on a semiconductor substrate and/or any other type of semiconductor body, and all such structures are contemplated as falling within the scope of the present invention. For example, the semiconductor substrate may comprise a semiconductor wafer (e.g., silicon, SiGe, or an SOI wafer) or one or more die on a wafer, and any epitaxial layers or other type semiconductor layers formed thereover or associated therewith.
While particular n- and p-type dopings are described herein according to NMOS technology, it is to be appreciated that one or more aspects of the present invention are equally applicable to forming a PMOS (generally, simply by reversing the n- and p-type dopings).
As best viewed in FIG. 1B, the FET 100 comprises a p-type substrate, and two spaced-apart n-type diffusion areas—one of which will serve as the “source”, the other of which will serve as the “drain” of the transistor. The space between the two diffusion areas is called the “channel”. The channel is where current flows, between the source (S) and the drain (D). A schematic symbol for an n-channel MOSFET appears to the left of FIG. 1B.
A thin dielectric layer is disposed over the substrate in the neighborhood of the channel, and a “gate” structure (G) is disposed over the dielectric layer atop the channel. (The dielectric under the gate is also commonly referred to as “gate oxide” or “gate dielectric”.) Electrical connections (not shown) may be made to the source (S), the drain (D), and the gate (G). The substrate may be grounded.
Generally, when there is no voltage applied to the gate, there is no electrical conduction (connection) between the source and the drain. As voltage (of the correct polarity, plus or minus) is applied to the gate, there is a “field effect” in the channel between the source and the drain, and current can flow between the source and the drain. This current flowing in the channel can be controlled by the voltage applied to the gate. In this manner, a small signal (gate voltage) can control a relatively large signal (current flow between the source and the drain).
An integrated circuit (IC) device may comprise many millions of FETs on a single semiconductor “chip” (or “die”), measuring only a few centimeters on each side. Several chips may be formed simultaneously, on a single “wafer”, using conventional semiconductor fabrication processes including deposition, doping, photolithography, and etching.
As best viewed in FIG. 1A, a trench, labeled “STI” surrounds a single FET 100. “STI” is short for silicon (or shallow) trench isolation, and generally involves forming (such as by etching into the surface of the substrate) a trench around the FET, and filing (such as by deposition) the trench with an insulating material such as silicon dioxide (commonly referred to simply as “oxide”).
Although only one STI trench (and a corresponding one FET) is shown in FIG. 1A, it should be understood that the trench may be formed by several intersecting, parallel trenches (like a tic-tac-toe board), as indicated by the dashed lines. The STI insulates (electrically isolates) the enclosed FET from other, neighboring FETs. The area within the trench is referred to as the active silicon region, and is often referred to as “RX”. Generally, there is minimum width (Wm) for the STI trench for each technology (the width of the trench has to be larger Wm for the technology), and the minimum width and RX width scales 70% for each generation. STI is omitted from the view of FIG. 1B, for illustrative clarity.
FIG. 2 is a cross-section of a portion of a semiconductor substrate 202 having a top surface 202a and a bottom surface 202b. Three STI trenches are illustrated (and labeled “STI”), and two active silicon regions (labeled “RX”) enclosed by the STR trenches are illustrated.
A given STI trench has sidewalls 204, and a bottom surface 206, and extends into the substrate 202, from the top surface 202a thereof, a distance “D” towards the bottom surface 202b of the substrate 202. The trench has a width dimension “W1” at the top surface 202a of the substrate 202, and a width dimension “W2” at its bottom end 206. The trench may be tapered, such as by an angle “a” of 5 degrees, resulting in the dimension W2 being slightly less than the dimension W1. A given active silicon area RX between two trenches may have a width of “W3”. A “pitch” dimension (also referred to as “RX-to-RX” distance, or pitch) may be defined as the distance “W4” between two identical points (such as the center of) two adjacent trenches. A cell well “CW” is generally formed in the substrate 202, between and extending slightly below the STI trenches. Exemplary dimensions for the STI and RX are:                W1=50-500 nm        W2=30-500 nm        W3=50-500 nm        W4=100-1000 nm.        
The CMOS technology is keeping the 70% scaling in both PC (gate) pitch and width to increase density and reduce cost. (For the next generation, most of the dimension scales 70% compared with previous generation. For example, the typical RX width at 65 nm generation is 500 nm, it will be 350 nm at 45 nm technology.) As the width is scaled down, the drive capability is reduced and it will affect the performance and circuit stability. One way to keep the same density and increase the device width is to reduce the STI width, but keep the same RX pitch (W4). But it will make it very difficult to fill the STI and also keep good isolation.